The present invention relates to a recording and/or reproducing apparatus and is applicable to a digital video tape recorder for recording and/or reproducing, for example, a digital video signal on a magnetic tape.
A known type of recording and reproducing apparatus for recording and/or reproducing a video signal of a high definition television system is the so-called digital video tape recorder (DVTR) in which an input video signal is converted into a digital video signal and recorded on a magnetic tape.
In particular, as shown in FIG. 1, this known digital video tape recorder (DVTR) 1 includes a recording system 2 in which a component video signal SO composed of red, green and blue signal S1, S2 and S3, or a component video signal S4 composed of a luminance signal S5 and R-Y and B-Y chrominance signals S6 and S7, having a bandwidth of, for example, 30 MHz, is supplied to a matrix circuit 3.
In the matrix circuit 3, if the component video signal S4 is the input signal, the luminance signal S5 and the R-Y and B-Y chrominance signals S6 and S7 included in the signal S4 are supplied to an analog to digital converter circuit 4. If the component video signal S0 is the input signal, it is converted into the component video signal S4 including the luminance signal S5 and the chrominance signals S6 and S7 and then supplied to the analog to digital converter circuit 4.
The analog to digital converter circuit 4 samples the luminance signal S5 in response to a first clock signal CK0 supplied thereto and a resulting digital luminance signal D1 having a bandwidth of 74.25 MHz is provided to a one-fourth times expansion circuit 5.
Further, the analog to digital converter circuit 4 samples the R-Y and B-Y chrominance signals S6 and S7 in response to the first clock signal CK0, the resulting R-Y and B-Y digital chrominance signals D2 and D3 each having a bandwidth of one half of 74.25 MHz are multiplexed in a multiplexer circuit 6 and the multiplexed signal is sent to the one-fourth times expansion circuit 5 as a multiplexed digital signal D4.
The one-fourth times expansion circuit 5 converts the digital luminance signal D1 and the multiplexed digital chrominance signal D4 provided to the expansion circuit 5 with a processing rate set by the first clock CK0 signal into a digital video data signal D5 composed of within each channel is a total of eight parallel data channels, four channels for each of the luminance signal and the multiplexed chrominance signal, with the signal in each channel having a processing rate set by a second clock signal CK1 whose frequency is one-fourth the frequency of the first clock signal CK0, so that the rate 18.5625 MHz. The resulting data D5 is sent to an interleave/parity adding circuit 7.
The interleave/parity adding circuit 7 interleave-processes the digital video data signal D5 and adds an outer parity code thereto and the resulting signal is supplied to a shuffling/parity adding circuit 8 as a digital video data signal D6.
The shuffling/parity adding circuit 8 shuffles the digital video data D6 and, after the latter is formed into blocks, adds an inner parity code thereto, and outputs the resulting signal to a SYNC-ID adding/coding circuit 9 as a digital video data signal D7.
The SYNC-ID adding/coding circuit 9 adds a synchronizing pattern and ID information including an identification code and an address to each block of the digital video data signal D7. The circuit 9 then divides the blocks of data into sets containing a predetermined number of blocks and adds a preamble to the end, and a postamble to the beginning of each set. The circuit 9 then codes the resulting signal with a 8--8 modulation system to produce a recording digital video data signal D8 which is sent to a parallel-serial converter circuit 10.
The parallel-serial converter circuit 10 converts the recording digital video data signal D8 into serial recording signals S10-S17 corresponding to eight channels and having a total data rate of 148.5 Mbps. The recording signals S10-S17 are supplied, respectively, to heads 13A-13H corresponding to the eight channels, the heads 13A-13H being mounted on a drum 12 around which a magnetic tape 11 is wound in the shape of an omega (.OMEGA.).
In the recording system 2 of the DVTR 1, the first clock signal CK0 is generated by a clock generator circuit 15 and supplied to the analog to digital converter circuit 4, the one-fourth times expansion circuit 5 and the multiplexing circuit 6.
The second clock signal CK1 is obtained by dividing the first clock CK0 by four by means of a 1/4 frequency divider circuit 16 and supplied to the one-fourth times expansion circuit 5, the interleave/parity adding circuit 8, the SYNC-ID adding/coding circuit 9 and the parallel-serial converter circuit 10 so that the recording signal processing circuits downstream from the one-fourth times expansion circuit 5 operate according to a timing provided by the second clock CK1.
Therefore, as shown in FIG. 2A, two sectors SEC1 and SEC2 corresponding to respective sectors are recorded in respective tracks on the magnetic tape 11 each of the heads 13A-13H over a period of two revolutions of the drum 12, which rotates at a rate of, 120 Hz so that one field of the input video signal SO (or S4) is recorded during the period of two revolutions.
A preamble P1 and a postamble P2 are attached to each sector SEC to indicate a beginning and an end thereof and a data recording area including 640 data blocks B1-B640 is formed between the preamble P1 and the postamble P2.
Each data block B has a total length of 226 words as shown in FIG. 2B, and includes a synchronizing pattern SYNC of 2 words in length, the identification and address data ID/ADRS of 4 words in length, followed by 220 words of data DT.
On the other hand, in a reproducing system 20 of the DVTR 1, reproduced signals S20 to S27 corresponding respectively to eight channels and at data rate of 148.5 Mbps are provided from the heads 13A-13H mounted on the drum 12 and are converted by a serial to parallel converter 21 into parallel signals which are sent to a TBC/de-shuffling circuit 22 as a reproduced digital video data signal D10 at processing rate of frequency 18.5625 MHz set by the second clock signal CK1.
The TBC/deshuffling circuit 22 performs a time-axis correction for the reproduced digital video data signal D10 supplied thereto to match the clock phase with the second clock signal CK1 and then performs error correction on the basis of the inner parity code. The circuit 22 also performs de-shuffling processing and sends a resulting digital video data signal D11 to an error correction circuit 23.
The error correction circuit 23 performs error correction on the digital video data signal D11 based on the outer parity code and sends a resulting digital video data signal D12 to a de-interleave/error correction circuit 24.
The de-interleave/error correction circuit 24 de-interleaves the digital video data signal D12 and performs interpolation etc. to correct errors which could not be corrected by error correction based on the inner and outer parity codes and outputs a resulting digital video data signal D13 to a time compression video image synthesizer circuit 25.
The time compression video image synthesizer circuit 25 time-compresses the digital video data signal D13 for the eight channels which was provided as mentioned previously and synthesizes the signal to produce a digital luminance signal D14 and a multiplexed digital chrominance signal D15 having bandwidths of 74.25 MHz corresponding to the first clock signal CK0.
The digital luminance signal D14 is supplied directly to a digital to analog converter circuit 26. The multiplexed chrominance signal D15 is divided by a division circuit 27 into R-Y and B-Y digital chrominance signals D16 and D17 each having a bandwidth of one-half of 74.25 MHz and the resulting signals are supplied to the digital to analog converter circuit 26.
The digital to analog converter circuit 26 converts the digital luminance signal D14 and the R-Y and B-Y chrominance signals D16 and D17 into respective analog signals and outputs a luminance signal S30 having a bandwidth of 30 MHz and R-Y and B-Y chrominance signals S31 and S32 each having a bandwidth of 15 MHz to a matrix circuit 28.
In the reproduction system 20 of the DVTR 1, the second clock signal CK1 generated by the 1/4 frequency divider circuit 16 is supplied to the serial to parallel converter circuit 21, the TBC/de-shuffling circuit 22, the error correction circuit 23, the de-interleave/error correction circuit 24 and the time compression video image synthesizer circuit 25 and the operations thereof are performed in response to the second clock signal CK1.
The first clock signal CK0 output from the clock generator circuit 15 is supplied to the time compression video image synthesizer circuit 25, the digital to analog converter circuit 26 and the divider circuit 27 so that those circuits operate in response to the first clock signal CK0.
The matrix circuit 27 is adapted to selectively output the luminance signal S30 and the R-Y and B-Y chrominance signals S31 and S32 directly as a component signal S33 or to produce red, green and blue signals S34, S35 and S36 from the inputted luminance signal S30 and the R-Y and B-Y chrominance signals S31 and S32 and to output the signals S34, S35 and S36 as a component video signals S37, thus reproducing the video signal recorded on the magnetic tape 11.
In the DVTR 1 as described above, the sampling frequency is selected as 4 fsc according to a quantization rule, etc., and, when the amount of data to be recorded is determined on this basis, the number of data block for one field of the video signal is not an integer.
For this reason, in the recording pattern discussed with respect to FIG. 2A, the interval between the block pulses which indicate a border between adjacent blocks B is discontinuous in each sector SEC, causing difficulties in signal processing in the recording system 2 and the reproducing system 20.
This problem becomes more severe with larger numbers of channels as in the above mentioned 8-channel recording and reproducing system.
More specifically, as shown in FIG. 3, for example, consider a DVTR in which four magnetic heads 32A-32D are arranged on a drum around which a magnetic tape 30 is wound in the shape of an omega (.OMEGA.) at intervals of 90.degree.. The magnetic heads 32A-32D rotate at a rate of 60 Hz, and video data corresponding to one field is converted into 4 parallel data channels and recorded as data sectors SD1, SD2, SD3 and SD4 (FIGS. 4B, 4D, 4F and 4H) each composed of a group of blocks, with respect to a vertical reference phase VR representing a border between adjacent fields as shown in FIG. 4A.
Since the number of blocks in each of the data sectors SD1, SD2, SD3, and SD4 in the respective channels within one field is not an integer, the respective block pulses BP1, BP2, BP3 and BP4 for the four channels have different phases as shown in FIGS. 4C, 4E, 4G and 4I. Consequently, circuits such as address circuits in the signal processing system and memories which process data block by block require four different respective circuit arrangements, causing the entire scale of the circuit to be large.
A similar problem occurs in the reproduction system. For example, when variable speed reproduction is to be performed, each of signals S20-S27 reproduced from the heads 13A-13H becomes a signal from another channel as shown in FIG. 6, since the respective heads 13A-13H (corresponding to the eight channels as mentioned previously with respect to FIG. 1) scan recording tracks T1, T2, T3, . . . , T8 on the magnetic tape 11 in an oblique manner as shown in FIG. 5.
Therefore, in this case, it is necessary to provide a channel converter circuit, for example, for exchanging the reproduced signals S20-S27 from the heads 13A-13H so as to provide normal outputs from the heads 13A-13H. Since there are phase difference between the block pulses BP1, BP2, BP3 and BP4 for the respective channels, even if the clock phases of the respective channels are matched with the first clock signal CK1 by means of the previously mentioned TBC/de-shuffling circuit 22, a correction circuit therefor is necessary, resulting in a complicated circuit design.